Compute Express Link and Gen-Z Consortiums have already announced their execution of a memorandum of understanding (MoU), describing a mutual collaboration plan between the two organizations there is a need for a coherence policy to update the cache entry in the second core’s cache otherwise, it becomes the cause of incorrect data and invalid results. Possible shakeouts/convergence is needed to move things forward. The major difference between them is that CXL is a master-slave architecture where the CPU is in charge, and the other devices are all subservient, while CCIX allows peer-to-peer connections with no CPU. The CXL specification’s founding promoter members included: Alibaba Group, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel, and Microsoft.īoth CXL and CCIX target the same problem. So to accelerate next-generation data center performance. When the second core attempts to read that value from its cache, it won’t have the most recent version unless its cache entry is invalidated. For example, imagine a dual-core processor where each core brought a block of memory into its private cache, and then one core writes a value to a specific location. Since each core has its cache, the copy of the data in that cache may not always be the most up-to-date version. Cache coherence refers to keeping the data in these caches consistent. Why is cache coherency required?įor higher performance in a multiprocessor system, each processor usually has its cache. Hence sharing memory with a cache brings a formidable technical challenge known as coherency, which is addressed by the compute express link (CXL). The growing trend towards heterogeneous computing in the data center means that, increasingly, different processors and co-processors must work together efficiently, while sharing memory and utilizing caches for data sharing. The article describing the proposed Questa VIP methodology for CXL is available for download here.The massive growth in the production and consumption of data, particularly unstructured data, like images, digitized speech, and video, results in an enormous increase in accelerators’ usage. There is a clear need for a wide range of pre-defined stimuli to ensure that you can achieve high coverage against your compliance goals.” The complexity of creating and managing thousands of individual test cases is not feasible within realistic schedule constraints. It argues that, VIP plays an important role because, “For verifying cache coherent systems verification plan A verification plan with stimulus generationīased on the specific use of Questa VIP, it describes each of these steps in detail and their implementation for a heterogenous data centre project using CXL.By comparison, another rival and broadly-supported connectivity technology, Cache Coherent Interconnect for Accelerators (CCIX), allows peer-to-peer connections (its supporters include AMD, Arm, IBM, Mellanox, Qualcomm, and Xilinx, as well as Huawei taking a dual role).Ī new technical article from Siemens EDA, “ Purging CXL Cache Coherency Dilemmas” sets out how to use verification IP – and the range of pre-defined stimuli, loggers, debug messengers and predictors within it – as part of a verification strategy built around four tenets. A further challenge with CXL, however, is that it has many different options for requests, responses and combinations of cache state.ĬXL is based on a PCIe Express 5.0 infrastructure to simplify implementation and the technology also takes a master-slave approach, with the CPU in charge. Verifying coherency in a CXL-fueled system faces the overarching problem of ensuring that the caches across multiple cores and their processors hold copies of the same high-risk data. Supporters include Alibaba, Cisco Systems, Facebook, Google, Huawei, Intel and Microsoft. Maintaining cache coherency across heterogeneous systems is becoming more difficult as applications around AI and machine learning, high-performance computing and next generation communications exact greater demands.Ĭompute Express Link (CXL) is a powerfully-backed technology that “enables high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices” in the datacenter. PCIe 6.0 gets verification IP as formal arrival approaches.Charting the path for machine learning in functional verification.
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